1. Field
Example embodiments relate to nonvolatile memory devices including one or more oxygen-deficient metal oxide layers and methods of manufacturing the same. Also, example embodiments relate to nonvolatile memory devices including one or more storage nodes in which one or more oxygen-deficient metal oxide layers is formed between at least one lower electrode and at least one data layer and methods of manufacturing the same.
2. Description of Related Art
A related art dynamic random access memory (DRAM) consists of a unit cell of 1T/1C (one transistor and one capacitor) structure. As the size of the DRAM decreases, the difficulty of manufacturing the transistor and/or capacitor increases, and thus, high yield manufacturing of DRAM cells is difficult. Therefore, it is desirable to develop a nonvolatile memory that may replace the related art DRAM. Attempts have been made to develop high integration density, low power consumption DRAMs, nonvolatile flash memories, and high operation speed static random access memories (SRAMs) as next generation memories. Such devices include phase change RAMs (PRAMs), nano floating gate memories (NFGMs), resistance RAMs (ReRAMs), polymer RAMs (PoRAMs), magnetic RAMs (MRAMs), and molecular electronic devices.
The ReRAM device may include a Metal Insulating Metal (MIM) structure using a metal oxide, and may show memory characteristics that, when an appropriate electrical signal is applied, the state of the MIM structure may change from a high resistance non-conductive state (i.e., an off-state) to a low resistance conductive state (i.e., an on-state), and vice versa. For the acronym MIM, M means upper and lower metal electrodes, and I means a data storage layer formed of an insulating material.
When switching is repeated in a storage node of a related art MIM memory cell structure, the distribution of the set and reset voltage values (Vset and Vreset) applied to the storage node may demonstrate a large deviation, and the distribution of the resistance values (Ron and Roff) of the storage node according to on and off states is not uniform.